A novel model for on-chip heat dissipation

Abstract

This paper presents an analytical model for on-chip heat dissipation in VLSI design. A chip and its test configuration also are developed to verify modeling results. The model and chip are representative of general IC packages. Our research shows that circuit location on a chip determines its default offset temperature and heat transport properties, which must be considered for accurate prediction of junction temperature and electrothermal analysis. The model yields insights about on-chip heat dissipation, which are very useful for mixed-signal VLSI designs and circuit reliability analysis.