A Novel Microprogrammed Reconfigurable Parallel VHBCSE Based FIR Filter for Wireless Sensor Nodes

Abstract

A micro-programmed Reconfigurable Parallel Finite Impulse Response (RPFIR) filter which can be used as subsystem in wireless sensor node is described in this work. High throughput is achieved using parallel processing and the power consumption is reduced using Vertical Horizontal Binary Common Sub expression Elimination (VHBCSE)-Reconfigurable Multiple Constant Multiplication (RMCM) based multiplier. The logical depth and logical elements are reduced using VHBCSE method. In the existing method, four 8*8 multipliers are used as two operand multiplier in the design of micro-programmed FIR. The two operand multiplier consumes more area and power when compared with Constant Multipliers (CM). The CM has been designed by using only adder, shifters and multiplexers, which consume less area and less power comparing with convention multipliers. The VHBCSE technique is used to find the redundant terms present within and adjutant coefficients, which in turn reduces the number of shifter, adder and multiplexer in the RMCM multiplier. This paper proposes the design of RPFIR filter based on VHBCSE technique which increases the throughput and reduces area and power consumption. It has been found that the power consumption of designed filter is reduced by 28% and throughput is increased by 4 times when compared with the existing FIR filters. Parallel processing used in this proposed system increases the throughput and VHBCSE technique reduces the redundant hardware and power dissipation. Experimental results are obtained for the proposed filter in FPGA platform and ASIC 180 nm technology. Finally, the results are compared with the existing works. The proposed parallel FIR filter will be suitable for implementation of a sensor node in ASIC and FPGA.