Abstract
In a multiprocessor system on chip (MPSoC) IC the processor is one of the highest heat dissipating devices. The temperature generated in an IC may vary with floor plan of the chip. This paper proposes an integration and thermal analysis methodology to extract the peak temperature and temperature distribution of 2-dimensional and 3-dimensional multiprocessor system-on-chip. As we know the peak temperature of chip increases in 3-dimensional structures compared to 2-dimensional ones due to the reduced space in intra-layer and inter-layer components. In sub-nanometre scale technologies, it is inevitable to analysis the heat developed in individual chip to extract the temperature distribution of the entire chip. With the technology scaling in new generation ICs more and more components are integrated to a smaller area. Along with the other parameters threshold voltage is also scaled down which results in exponential increase in leakage current. This has resulted in rise in hotspot temperature value due to increase in leakage power. In this paper, we have analysed the temperature developed in an IC with four identical processors at 2.4 GHz in different floorplans. The analysis has been done for both 2D and 3D arrangements. In the 3D arrangement, a three layered structure has been considered with two Silicon layers and a thermal interface material (TIM) in between them. Based on experimental results the paper proposes a methodology to reduce the peak temperature developed in 2D and 3D integrated circuits .
Highlights
With the development of newer technologies, more devices have been integrated into a single chip
The first step in the design of such architecture is to find out the heat dissipating devices and analyse the temperature developed in different floorplans
3D integration has got many challenges associated with it. 3D circuits are more susceptible to noise and stress failures due to rise in temperature. As this affects the reliability of the chip very much a thermal aware floorplan is of prime importance
Summary
With the development of newer technologies, more devices have been integrated into a single chip. The stacked devices in different layers communicate through special interconnects called Through Silicon Vias (TSV). The first step in the design of such architecture is to find out the heat dissipating devices and analyse the temperature developed in different floorplans. We have done experiments to find out the extent to which the temperature can shoot up in 2D and 3D IC with four processors with the help of Hotspot simulator. This simulator takes the files with floorplan and power of devices as inputs. Each of them consumed 50.9 Watt power in the active mode
Sign-in/Register to view highlights & summary Sign-in/Register to access full text options 
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callMore From: International Journal of VLSI Design & Communication Systems
Disclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
