A novel methodology for hybrid mask AF generation for 22 and 15nm technology

Abstract

Mask AF (AF), both printable (PRAF) and non-printable - or sub-resolution - AF (SRAF) have been part of the established lithography and RET/OPC toolkit for achieving a manufacturable process window, for several technology generations. Deployment of AF onto a mask for a full product or test-chip layout has been traditionally rule-driven, i.e. based on look-up tables of critical feature sizes and corresponding AF, with specified dimensions and at specified distances. The number of AF per given layout main feature, the set of AF dimensions (widths, heights, etc.) and the distances (placements) from the main features are collectively referred to as the AF Rules Set. The identification of the optimal parameters values in an AF Rules Set (or the optimal AF Rules, for short) is a fundamental problem in process technology development for semiconductor manufacturing, which is typically being addressed by a mixture of heuristic parametric searches and lithographic simulations. This approach produces a limited number of usable AF rules (mainly for 1D layout configurations) and often results in insufficient coverage for 2D cases. This paper introduces a novel methodology for the determination of an optimal AF Rules set, which results in a greatly superior coverage of layout configurations (both 1D and 2D) and quantitatively verifiable larger common process window. The methodology utilizes an inverse lithography simulation step, followed by computational geometry analysis and filtering and finally automated rules extraction. The computational flow, which has been implemented for 22nm process development, delivers an order of magnitude more rules (i.e. from few tens to several hundred), and often generates non-intuitive 2D rules which could not have been discovered by heuristic search alone. The presented results illustrate the superior performance of this technique particularly in the case of contact and metal layers at 22nm. Potential extendibility of this approach for the 15nm node is also discussed.