A novel methodology for accelerating bitstream relocation in partially reconfigurable systems

Abstract

Xilinx Virtex FPGAs offer the possibility of Partial Reconfiguration (PR). Arbitrary tasks can be allocated and de-allocated onto FPGA without system interruption. However, mapping a task to any available PR region requires a unique partial bitstream for each partition, hence reducing memory storage requirements. In recent years, an interest on overcoming this problem has lead to the concept of Partial Bitstream Relocation (PBR). The principle is to perform bitstream modification to map it to different regions. However, PBR consumes scarce resources in hardware implementations, and introduces a prohibitive time overhead when done in software. In order to find the best compromise between these approaches, we have developed the OORBIT tool (Offline/Online Relocation of Bitstreams) which accelerates the relocation time considerably. The methodology consists, firstly, in an offline bitstream modification phase which generates relocatable bitstreams including additional relocation data. Afterwards, online relocation is performed by a simple substitution of the initial location data by those calculated offline, corresponding to the target PRR. In this paper, we provide a detailed description of our methodology, emphasizing its interaction with the newest Xilinx Partition PR Design Flow, which results in major changes compared to previous efforts. Finally, a performance comparative analysis is detailed to highlight the significant relocation speedups that might help in making the relocation more amenable.