A novel method for reduction partial product tree in ternary multiplier

Abstract

In this paper, a new method for multiplying two n-trit numbers using CNFET and ternary logic is introduced. The carry resulted from the ternary multiplier never takes the value of two and is always zero or one. In this paper, this feature of the carry is used to construct two novel capacitive and transistor structures for reducing the partial product tree. These structures simultaneously improve the power consumption and latency, and the higher is the number of the trits of the two multiplied numbers, the increase in this improvement will be more. In this paper, on average, the proposed capacitive structure improves power consumption, latency and PDP as much as 26.72%, 9.74% and 33.8% respectively compared to the original structure. This improvement for the proposed transistor structure will be changed to 26.67%, 8.77% and 33.04% respectively. The reason for the lower improvement in the transistor structure is the overhead in this structure, which will be examined.