Abstract
An on-chip debugging method based on the RISC-V processor is introduced, which simplifies the complicated debugging operation into instructions and improves the debugging efficiency effectively. The method adopts a JTAG interface to realize the debugging functions of the processor, such as running control, software breakpoint, hardware breakpoint and single-step execution. The method was verified by simulation at the RTL level, and the logic synthesis was carried out in SMIC 180nm process library.
Highlights
RISC-V, incubated at the University of California, Berkeley, is a fifth-generation instruction set architecture based on the principle of the reduced instruction set
Most of the current instruction set architectures are protected by patents, which discourages small companies and limits the development and innovation of the processor industry
Debugging design is very important to promote the use of RISC-V processors, which can effectively promote the development of RISC-V processor ecology
Summary
RISC-V, incubated at the University of California, Berkeley, is a fifth-generation instruction set architecture based on the principle of the reduced instruction set. Most of the current instruction set architectures are protected by patents, which discourages small companies and limits the development and innovation of the processor industry. The RISC-V's open source and free feature have injected new vitality into the development of processors. With the increase of processor area and frequency, the development and debugging of software become more complicated, and the requirement of debugging means is higher and higher[1]. Good debugging features are designed to help software developers quickly locate errors. Debugging design is very important to promote the use of RISC-V processors, which can effectively promote the development of RISC-V processor ecology. The common debugging operations are simplified into instructions, avoiding the input of a large amount of data through the shift register chain
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