A Novel Method for Encoding Data Firmness in VLSI Circuits

Abstract

The number of tests, corresponding test data volume and test time increase with each new fabrication process technology. Higher circuit densities in system-on-chip (SOC) designs have led to drastic increase in test data volume. Larger test data size demands not only higher memory requirements, but also an increase in testing power and time. Test data compression method can be used to solve this problem by reducing the test data volume without affecting the overall system performance. The original test data is compressed and stored in the memory. Thus, the memory size is significantly reduced. The proposed approach combines the selective encoding method and dictionary based encoding method that reduces test data volume and test application time for testing. The experiment is done on combinational benchmark circuit that designed using Tanner tool and the encoding algorithm is implemented using Model -Sim