Abstract
A new structured cell is proposed for the logic compatible Merged DRAM gain cell capable of reducing the cell size to almost one transistor area and with small increase in process steps. It can drastically improve “1” and “0” states separation due to the JFET effect of n channel region between two p+ gate regions. This new cell does not require new materials nor new equipments. Non-destructive read-out (NDRO) is possible resulting in higher speed read cycle.
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