A novel major/minor loop bubble memory chip organization for high performance without block replication

Abstract

Bubble memory chips were originally organized with reentrant major loops, but presently the tendency is towards a block replicate organization, because of the latter’s better performance and data integrity protection. However, as shown in this paper, all the advantages of the block replicate organization, and more, can be realized by a novel organization that still uses reentrant major loops and no block replication. This organization features a direct path from the generator to the detector, two replicate/swap gates coupling that path to a pair of reentrant major loops, and double period swap gates coupling the major loops to the minor loops. As a result, average access and request cycle times are reduced to 65% and 75%, respectively, of their previous best values for the same chip capacity, and potential volatility problems are eliminated.