Abstract
Problem statement: High speed operational amplifier is always an on-go ing research topic since major high speed application are needed. Approach: A two-stage operational amplifier (op amp) is designed, simulated and fabricated using a UMC 0 .5 µm 2P2M CMOS technology. Results: This chip includes a compensation technique to ensure st ability and zero systematic input-offset-voltage. The fabricated chip achieves a 84 dB open loop gain , a 24 V µS -1 slew rate, a 84 dB CMRR utilizing a capacitive load of 5 pF, a 30 MHz unity gain frequency and consumes 2.8 mW from a 2.5 V power supply. Conclusion: The proposed chip, which is the first available CMO S operational amplifier in Jordan as the authors are aware, is we ll-suited to low-voltage applications since it does not require cascade output stages.
Highlights
The two-stage circuit architecture has historically been the most popular approach for both bipolar and CMOS op amps, where a complementary process that has reasonable n-type and p-type devices is available (Roberge, 1975)
The two-stage op amp is characterized by its excellent performance when resistive loads need to be driven (Steininger, 1990)
The dc offset voltage is reduced by changing the width of transistor M6 (Wu and Nabhan, 2004), taking into consideration that this can be done by changing the widths of transistors M7, M5 and M4
Summary
The two-stage circuit architecture has historically been the most popular approach for both bipolar and CMOS op amps, where a complementary process that has reasonable n-type and p-type devices is available (Roberge, 1975). This study includes a CMOS version of a two-stage op amp, a bipolar version is similar but slightly more complicated. The two-stage op amp is characterized by its excellent performance when resistive loads need to be driven (Steininger, 1990). A two-stage op amp with a high CMRR and a high unity gain frequency is proposed and analyzed. The proposed op amp includes three cascaded stages-two gain stages and a unity-gain output stage necessary for driving resistive loads. The proposed circuit has an open-loop gain of 84 dB, a CMRR of 84 dB, a slew rate of 24 V μS−1, a unity-gain frequency of 30 MHz and consumes 2.8 mW
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