A novel low-overhead fault tolerant parallel-pipelined FFT design

Abstract

As soft errors become a significant threat to modern electronic systems, the first priority of protection against soft errors should be decreasing resource consumption. This brief proposes a novel low-overhead fault tolerant FFT design, combining modified reduced precision redundancy (RPR) method and error correction codes (ECCs). RPR can lower the hardware overhead when compared with traditional full-precision redundancy techniques, especially when resource of the original design is huge. ECCs are cost-efficient for achieving fault tolerance on our parallel-pipelined FFT. As an example, an FPGA implementation of a four-channel 16K-point FFT is presented, which demonstrates that the proposed scheme can further reduce the overhead of fault tolerance designs.