Abstract
The pursuit of continuous scaling of electronic devices in the semiconductor industry has led to two unintended but significant outcomes: a rapid increase in susceptibility to radiation induced errors, and an overall rise in power consumption. Operating under low voltage to reduce power only aggravates radiation related reliability issues. The proposed “SEU Hardening Incorporating Extreme Low Power Bitcell Design” (SHIELD) addresses these two major concerns simultaneously. It is based on the concept of gating the conventional cross-coupled inverters while introducing a novel “cut-off” network. This creates redundant storage nodes and eliminates the internal feedback loop during radiation particle impact. The SHIELD bitcell tolerates upsets with charge deposits over 1 pC. Simulations confirm its advantages in terms of leakage power, with more than twofold lower leakage currents than previous solutions when operated at a 700mV supply voltage in a 65 nm process. To validate the bitcell’s robustness, several test cases and special concerns, including multiple node upsets (MNU) and half-select, are examined.
Highlights
The scaling of transistor dimensions in recent years has led to an increase in power consumption, mainly due to the increase in leakage currents
The read operation can result in a bit-flip if the pull down network (PDN) is weaker than the access transistor at the “0” holding node
SHIELD bitcell is fully immune to single event upset (SEU) induced in a natural space environment
Summary
The scaling of transistor dimensions in recent years has led to an increase in power consumption, mainly due to the increase in leakage currents. Correction is typically done by Error Correction Codes (ECC) and prevention by Triple Modular Redundancy (TMR) [6] These solutions use standard bitcell architecture and standard process and are technology independent, they have many drawbacks in terms of additional delays and decreased efficiency related to the increased probability of multi-bit errors at small size scales [7]. Circuit level solutions, such as DICE [9] and Quatro 10T [10], can efficiently increase SEU tolerance These solutions have flaws in the form of high power consumption and area inefficiency due to high transistor count. It was shown that SHIELD tolerates upsets with charge deposits over 1 pC with more than twofold lower leakage currents than previous solutions when operated at a 700 mV supply voltage in a 65 nm process.
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