A Novel Interface Circuit for Capacitive Sensors Using Correlated Double Sampling Demodulation Technique

Abstract

The capacitive readout circuit with CMOS-base (complementary metal oxide semiconductor) MEMS (microelectromechanical systems) devices for micro sensor applications has been developed. This study presents a novel method to make a low noise CMOS-MEMS readout circuit that can prevent the noise from electronic components and reduce the AC distortion due to sensing capacitance mismatch. Here, a significant method of correlated double sampling (CDS) technique can be employed to the proposed sample-and-hold demodulation structure which can diminish the problem of capacitance mismatch. The read out circuit is fabricated using 0.35 mum 2P4M CMOS process for demonstration. Simulation result indicates that the sensing circuits can achieve low power consumption of 3.78 mW with a sampling frequency of 4 MHz, and the overall sensitivity of the proposed circuit is 155 mV/fF. Also, a spurious free dynamic range (SFDR) of 39.4 dB is simulated in this design and shows a great linearity.