A novel high-speed counter with counting rate independent of the counter's length

Abstract

Counters are among the basic blocks in every digital system. We propose a novel high-speed counter with a constant counting rate, independent of its length. Exploiting special features of the binary arithmetic system and adopting prescaling techniques, a segmented counter architecture is introduced. Particularly, to realize a counter of any length properly, two designed modules of four-bit counter are used in a systolic manner. The counting rate is bounded by the delay of two basic gates of three inputs plus the delay of a T F/F. In AMS 0.6 /spl mu/m technology a maximum of 430 MHz counting frequency is achieved.