A novel high-rate hybrid window ADC design for monolithic digitally-controlled DC-DC converters

Abstract

We propose a novel high-rate low-power hybrid window analog-to-digital converter (HWADC) for monolithic digitally-controlled switched-mode dc-dc converters. Conventional Window ADCs are generally based on either voltage-controlled delay lines or ring oscillators. These ADCs usually have a small window size (input voltage range) and a low sampling rate (<10 MHz) in order to reduce the required IC area and the power dissipation. The proposed HWADC employs a novel hybrid architecture that is a hybrid of delay-lines and ring-oscillators. The HWADC can achieve a large window size with a very high conversion rate, a small IC area, and low power dissipation. Further, the HWADC operates entirely based on digital logic, and is simple to realize using digital cells. The proposed HWADC is designed using a 65 nm CMOS process. Its IC area is 0.005 mm2. Simulation results at 1.2 V supply show that the HWADC can achieve a window size up to 1.2 V (configurable from 0.7 V to 1.9 V) at 250 MHz conversion rate and ∼770 μW power dissipation. At the maximum window size of 1.2 V, the quantization step is 50 mV, or equivalently, a resolution of ∼4.5 bits.