Abstract
Leakage power has become a critical issue of today's CMOS circuit design with technology scaling. This paper analyzes the stack effect of leakage power in CMOS circuits, and presents an efficient heuristic approach for bounding maximum and minimum leakage power, which is based on an improved simulated annealing algorithm (ISA). Experiments on ISCAS-85/89 benchmark circuits show that this approach can improve remarkably on previous random simulation algorithm and genetic optimization algorithm.
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