A novel hetero-junction Tunnel-FET using Semiconducting silicide–Silicon contact and its scalability

Abstract

A new type of silicon-based Tunneling FET (TFET) using semiconducting silicide Mg2Si/Si hetero-junction as source-channel structure is proposed and the device simulation has been presented. With narrow bandgap of silicide and the conduction and valence band discontinuous at the hetero-junction, larger drain current and smaller subthreshold swing than those of Si homo-junction TFET can be obtained. Structural optimization study reveals that low Si channel impurity concentration and the alignment of the gate electrode edge to the hetero-junction lead to better performance of the TFET. Scaling of the gate length increases the off-state leakage current, however, the drain voltage (Vd) reduction in accordance with the gate scaling suppresses the phenomenon, keeping its high drivability.