A novel gate grading approach for soft error tolerance in combinational circuits

Abstract

Continuous reduction in the minimum feature size of semiconductor devices and the supply voltages in advanced VLSI logic circuits has made those circuits more susceptible to soft errors. Hence, several fault tolerance techniques have been proposed in the literature to protect combinational circuits against single event transients (SETs). These fault tolerance techniques are based mainly on hardware redundancy and therefore they come at the cost of significant area and power overhead. In this paper, a novel gate grading approach is proposed to prioritize gates based on their influence on the circuit's reliability. Specifically, different masking factors are taken into account and the gates with the lowest masking capabilities are identified so that they can be hardened first. Since the gates with higher priorities affect the circuit's reliability more significantly, protecting those gates increases the circuit's reliability with the least required area and power overhead.