Abstract
A novel full differential double sampling circuit is presented in the paper. The traditional full differential single sampling circuit is compared with the proposed full differential double sampling one to show that the latter has more efficiency and higher speed The proposed full differential double sampling circuit is designed in TSMC 0.18μm CMOS process technology. The simulation results show that the SFDR of the proposed full differential double sampling circuit is 81.36dB at 200MS/s. Further simulations show that the proposed full differential double sampling circuit has twice better performance than the traditional one.
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