A Novel FinFET Device with a Four-Period Vertically Stacked SiGe/Si Fin

Abstract

In this work, a novel four-period vertically stacked SiGe/Si FinFET is demonstrated to further boost the electrical performance of the FinFET device. The stacked SiGe/Si fin structure was fabricated successfully by developing the stacked SiGe/Si epitaxial growth and etching processes. Compared with the conventional SiGe channel FinFET, the driven current ION and ION/IOFF ratio of this novel FinFET device increased by 1.6 and ~10 times, respectively. Meanwhile, its subthreshold slope (SS) was improved from 149mV/dec to 90 mV/dec. The improvement of electrical performance can be attributed to the high quality SiGe layer, increased effective channel width, and excellent surface interface properties throughout the whole fabrication process. More importantly, after employing an optimized O <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</inf> passivation technique, its SS and ION/IOFF ratio can be further improved to 75mV/dec and $5\times{10}^{6}$, respectively. The above results strongly suggest that this novel stacked SiGe/Si channel FinFET device is a promising candidate for future technology nodes.