A Novel Feasibility Test for Energy Minimization of Real-Time Mixed Task Sets for DVS-Enabled Uniprocessor System

Abstract

With advancements in computing and communication technologies on mobile devices, the performance requirements of embedded processors have significantly increased, resulting in a corresponding increase in its energy consumption. Dynamic scaling of operating voltage and operating frequency has a strong correlation to energy minimization in CMOS real-time circuits. Simultaneous optimization of ([Formula: see text], [Formula: see text] pairs under dynamic activity levels is thus extensively investigated over several years. The supply voltage is tuned dynamically during runtime (DVS), with a fixed threshold voltage, to achieve energy minimization. This work addresses the issue of maximizing the energy efficiency of real-time periodic, aperiodic and mixed task sets, in a uniprocessor system, by developing a novel task feasibility methodology, with a novel processor performance-based constraint, to generate the optimal operating supply voltage to the individual task of task sets. The energy minimization of real-time mixed task sets is formulated as Geometric Programming (GP) problem, by varying frequency for periodic tasks sets and keeping fixed frequency for aperiodic tasks set, over a range of task sets and hence computing optimal operating voltages. Simulation experiments show energy savings on the cumulative basis of 50%, 38% and 29% for periodic, aperiodic and mixed task sets, respectively, based on the processing timing constraints of task sets.