A novel elevated source/drain PMOSFET formed by Ge-B/Si intermixing

Abstract

Driven by strain relaxation, the rapid thermal annealing (RTA) of B-doped Ge on an Si substrate forms graded Si/sub 1-x/Ge/sub x/ layers with B confined inside. Based on this observation of Ge-B/Si intermixing, a novel elevated source/drain (S/D) PMOSFET fabrication process is proposed. The new process consists of three simple steps: (a) selective Ge deposition in S/D regions by conventional LPCVD, (b) B implantation, and (c) RTA for Ge-B/Si intermixing to form S/D extensions to the channel. Fabricated PMOSFETs with sub-100 nm gate lengths display excellent short channel performance.