A novel dual-reference sensing scheme for computing in memory within STT-MRAM

Abstract

With the rapid development of the Internet of Things and artificial intelligence, it is more and more difficult for the existing hardware structure to process billions of data. In conventional Von-Neumann architectures, the well-known “memory wall” becomes a critical barrier to limit bandwidth. In order to solve this problem, computing in memory (CIM) within STT-MRAM (Spin Transfer Torque Magnetic Random Access Memory) emerges gradually. However, CIM requires multiple memory units in parallel, resulting in higher reading error rate. In this paper, a novel dual-reference sensing scheme (NDRS) is proposed for hybrid CMOS/MTJ logic circuits. By exploiting novel precharge scheme and adding inverter to amplify signals, NDRS scheme can improve CIM reliability significantly. Under the 40 nm technology node and a physics-based MTJ compact model, 1000 times Monte Carlo simulation shows that AND logic operation error rate is ∼7.42% and OR logic operation error rate is ∼2.67%.