A Novel Dual-Modulus 2.8 GHz Divide-by-127/128 Prescaler Using Pull Down Transistor in 0.35 μ m CMOS Technology

Abstract

Design of high divide-by-value dual-modulus prescaler remains a challenge in CMOS realization for high speed operation. Prior arts for dual modulus prescaler either divide by a low divide-by-value or cannot operate at high speed. The proposed topology is suitable for high divide-by-value operation at high speed.