A novel "double-decker" flip-chip/BGA package for low power Giga-Hertz clock distribution

Abstract

Clock distribution network design directly affects the performance of synchronous digital systems. Traditional single source on-chip clock distribution techniques become increasingly difficult as clock frequencies approach 1 GHz and beyond. We propose a multiple source clock distribution architecture and a novel double-decker flip-chip/BGA package to solve future GHz clock distribution problems. Analysis indicates that our new clock distribution approach can achieve low clock skew and sharp clock edges for frequency up to a few GHz over a large die area. The power dissipation of the clock distribution network is also found to be significantly smaller in our new clock distribution approach compared to traditional techniques.