A Novel Double-Gate MOSFET Architecture as an Inverter

Abstract

In this work, a novel structure of a double-gate MOSFET is proposed and simulated. The CMOS inverter action in a single device realized by combining p-mode and n-mode MOS transistors is presented. The main advantage of the proposed device is fewer transistors for implementing sequential and combinational circuits. The significant reduction of the transistors, while designing a combinational circuit, will enhance the electronic industry with less power consumption. In our proposed device, a single substrate is used in comparison to the conventional CMOS inverter. The proposed device reduces short channel effects at lesser channel length. For Lg = 50nm, the proposed device, as an inverter, offers a unique VTC curve, SNM, V-curve along with sound values of performance parameters individually for p-mode and n-mode. A significant reduction in the junctions, wells and oxide regions can be seen from the proposed inverter design. Besides the performance of the device, the fabrication steps and the layout of the DGMOSFET-I are also presented in work.