A novel digital calibration with low complexity for pipelined ADC

Abstract

A novel digital background calibration technique is presented which is applied to high resolution high speed pipelined ADC. This technique is based on the structure of 2.5-bit/stage switched-capacitor multiplying-digital-to-analog converter (MDAC). Several random arrays adopted to carry the error information are introduced in the first two MDACs. Signal correlation theory is used to pick up the error in the digital domain through accumulation and average. Finally the error is fed back to the digital output for compensation. The arithmetic is simple and flexible, which can work at high frequency. Meanwhile it never interrupts the normal outputs. The FPGA verification shows that after calibration ENOB increases from 8.5 bit to 13.7 bit, and the level of SFDR improves from 57.9 dB to 108.4 dB.