A novel design of nanometric reversible cache memory

Abstract

In this paper we proposed a reversible cache memory for the first time. Four formulas for computing quantum cost, number of garbage outputs, number of constant inputs and number of gates of the proposed reversible circuit are suggested. These formulas can be used for any type of cache memory with any number of address bits and cache lines or cache blocks. Moreover we proposed a fault tolerant reversible cache memory and then formulas for computing the parameters of this circuit are also suggested. Key words: Reversible logic, cache memory, quantum cost, faults tolerant.