A Novel Data-Path for Accelerating DSP Kernels

Abstract

A high-performance data-path to implement DSP kernels is proposed in this paper. The data-path is based on a flexible, universal, and regular component to optimally exploiting both inter- and intra-component chaining of operations. The introduced component is a combinational circuit with steering logic that allows in easily realizing any desirable complex hardware unit, called template; so that the data-path’s performance benefits by the intra-component chaining of operations. Due to the component’s flexible and universal structure, the Data Flow Graph is realized by a small number of such components. The small numbers of the used components coupled with a configurable interconnection network allow adopting direct inter-component connections and optimally exploiting any inter-component chaining possibility over to the existing template- based methods. Also, due to universal and flexible structure of the component, scheduling and binding are accomplished by simple, yet efficient, algorithms achieving minimum latency at the expense of an area penalty and a small overhead at the control circuit and clock period. Results on DSP benchmarks show an average latency reduction of 20 path.KeywordsClock CycleDigital Signal ProcessingRegister BankClock PeriodCombinational CircuitThese keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.