Abstract

A novel technique to efficiently increase the resolution of coherent digital sweep oscillators based on look-up-table (LUT) methods is proposed. The increase in resolution measured in terms of sweep rates is achieved while maintaining very low levels of spurious harmonic distortion. The proposed technique increases the LUT length to a level at which the spurious harmonic distortion is negligible. The proposed technique is based on partitioning the address register into three sets and dividing the available LUT length into five smaller tables addressed according to the content of the three address register sets. The proposed technique is simulated and its performance is compared with that of the known sweep oscillators. The simulation results show that the proposed technique is superior to all sweep oscillators reported in the literature.

Highlights

  • Coherent digital sweep oscillators in which both the frequency and phase of the sweep signal arc specified for all time are essential elements in many applications

  • We propose a novel technique to efficiently achieve extremely low sweep rates and at the same time reduce the spurious harmonic distortion associated with fractional addressing of the LUT

  • The proposed technique has the advantage of increased sweep resolution and reduced spurious harmonic distortion over all sweep oscillators reported in the literature and its hardware implementation is much simpler than the sweep oscillator in [10]

Read more

Summary

A NOVEL COHERENT DIGITAL SWEEP OSCILLATOR WITH EXTREMELY LOW

A novel technique to efficiently increase the resolution of coherent digital sweep oscillators based on look-up-table (LUT) methods is proposed. The increase in resolution measured in terms of sweep rates is achieved while maintaining very low levels of spurious harmonic distortion. The proposed technique increases the LUT length to a level at which the spurious harmonic distortion is negligible. The proposed technique is based on partitioning the address register into three sets and dividing the available LUT length into five smaller tables addressed according to the content of the three address register sets. The proposed technique is simulated and its performance is compared with that of the known sweep oscillators. The simulation results show that the proposed technique is superior to all sweep oscillators reported in the literature

INTRODUCTION
REVIEW OF PREVIOUS SWEEP OSCILLATORS
THE PROPOSED SWEEP OSCILLATOR
Bit Width Requirements
Performance Calculations
SIMULATION RESULTS
CONCLUSION
Full Text
Published version (Free)

Talk to us

Join us for a 30 min session where you can share your feedback and ask us any queries you have

Schedule a call