A Novel Co-design Methodology for Optimizing ESD Protection Device Using Layout Level Approach

Abstract

This work explores the new ESD (electrostatic discharge) protection design methodology for high speed off-chip communication ICs (Integrated Circuits). We propose novel methodology which describes the optimized design prediction of ESD protection device under HBM (Human Body Model) stress condition. Furthermore, we have discussed the ESD-I/O circuit interaction and improved the ESD circuit robustness by varying the various layout parameters and minimizing the parasitic capacitance of the protection device. Here, GG-NMOS (Gate Grounded NMOS) is taken as an ESD protection device. Moreover, LVDS (Low Voltage Differential Signaling) driver circuit is used as test circuit, where we compared the impact of capacitance due to protection device on circuit performance. The second breakdown triggering current (It2) which can be considered a metric of ESD robustness, is dependent on the drain to gate contact spacing (DCGS). We show that spacing optimization effectively elevates It2 by increasing the ballasting behavior and uniformity in current distribution while causing only a marginal increment in parasitic capacitance.