A novel clocking technique for VLSI circuit testability

Abstract

Scan-testable digital designs have a special `scan' operating mode to set and read the states of flip-flops in the circuit. All previous scan-testable design implementations required at least one additional input pin to specify either scan or normal operating mode, and this mode specification signal had to be routed to every flip-flop. A new clocking structure is described which eliminates these requirements for certain designs with static flip-flops that are controlled by two independent signals (master clock and slave clock). This is possible because, in normal circuit operation, the master and slave clocks are never simultaneously active. The new clocking structure uses the `all clocks active' condition to specify the scan mode. Implementation of the concept is discussed in detail for two-clock circuits. Single-clock circuits can be modified to use this scheme, and the results for this class of design are also presented.