A novel bit‐line direct‐sense circuit that uses a feedback system for high‐speed Flash memory

Abstract

AbstractIn this paper, a novel bit‐line direct‐sense circuit is proposed in order to realize high‐speed Flash memory. The sense circuit proposed in this paper controls the drivability of the bit‐line charging transistor by means of a feedback technique. In this way, it becomes possible to charge the bit‐line at high speed so that high‐speed readout becomes possible. In spite of complexity in the circuit configuration, the increase of the chip area size is so small as to be negligible. The possibilities of oscillation in the feedback system are analyzed. It is demonstrated that the proposed sense circuit is stable. Hence, the proposed sense circuit can realize high‐speed stable readout of Flash memory. © 2006 Wiley Periodicals, Inc. Electron Comm Jpn Pt 2, 89(8): 1–8, 2006; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/ecjb.20263