A novel approach to testing LUT-based FPGAs

Abstract

A novel approach to testing look-up table (LUT) based field programmable gate arrays (FPGAs) is proposed in this paper. A general structure for the basic configurable logic array blocks (CLBs) is assumed. We group k CLBs in the column into a cell, where k denotes the number of inputs of a LUT. The whole chip is partitioned into disjoint one-dimensional arrays of cells. We assume that in each linear array, there is at most one faulty cell, and a faulty cell may contain multiple faulty CLBs. For the LUT, a fault may occur at the memory matrix, decoder, input or output lines. The stuck-on and stuck-off fault models are adopted for multiplexers. Our idea is to configure the cells to make each cell function bijective. In order to detect all faults defined, k+1 configurations are required. For each configuration, a minimal complete input sequence is applied to the leftmost cells of each linear array and the outputs of the rightmost cells can be observed. The input patterns can be easily generated with a k-bit counter and the resulting fault coverage is 100%.