Abstract
This research paper deals with Static Random Access Memory (SRAM) design opportunities for low power consumption. Initially, four leakage current components are reviewed. Subsequently, some leakage current reduction techniques are discussed for a 6T SRAM cell. Based upon the configurations, a double Angered latch is analyzed and compared with a single finger latch that exhibits significant reduction in sub threshold leakage current. In this paper, the reduction of sub threshold leakage currents are demonstrated up to 12160 nA for 64K byte memory.
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