Abstract
This research paper deals with Static Random Access Memory (SRAM) design opportunities for low power consumption. Initially, four leakage current components are reviewed. Subsequently, some leakage current reduction techniques are discussed for a 6T SRAM cell. Based upon the configurations, a double Angered latch is analyzed and compared with a single finger latch that exhibits significant reduction in sub threshold leakage current. In this paper, the reduction of sub threshold leakage currents are demonstrated up to 12160 nA for 64K byte memory.
Sign-in/Register to access full text options 
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
