A Novel Approach to Improve the Performance of Charge Plasma Tunnel Field-Effect Transistor

Abstract

A distinct approach is presented for realizing charge plasma tunnel field-effect transistor (CP TFET) wherein p+ substrate is taken as silicon film and then metal electrodes with specific work functions are deposited over the silicon film to accumulate n+ drain and intrinsic channel regions. This creates abruptness and reduces the barrier at the source/channel interface of CP TFET, which improves the dc characteristics of the device. Furthermore, the drain electrode is separated into two sections and applied with dual work function, which reduces the ambipolar behavior, parasitic capacitance, and enhances radio frequency parameters. The crux of the script is to advance the performance of the device while maintaining the classical CMOS fabrication flow with its inherent advantages by using p+ substrate initially. To analyze the performance, a comparison between conventional CP TFET and dual drain electrode CP TFET (proposed) is shown at the simulation level. Optimization of length and workfunction of the section of drain electrode adjacent to the channel is demonstrated to assess the desired ON-current and ambipolarity of the device. Furthermore, the device performance is examined with the application of multigate work function and heterogate dielectric engineering to achieve more improvements in device performance.