A Novel Approach to Design Braun Array Multiplier Using Parallel Prefix Adders for Parallel Processing Architectures

Abstract

Multipliers play a important role in current signal processing chips like DSP and general purpose processors and applications. In such high performance systems addition and multiplication operations are fundamental and most used arithmetic operations. Some case study shows that more than 70% of DSP algorithms and in microprocessor operations perform addition and multiplication. Hence these operations dominate the execution time. To meet the processing speed demand, the design of multipliers and adders plays a vital role. Low power consumption has consumption has became a major issue in design of multiplier. To reduce the power consumption, the components used in the design must be drastically reduced and in parallel it should not degrade the other performance metric. In this paper we are proposing a new architecture to design multiplier using parallel prefix adders. The Parallel Prefix Adder (PPA) have fast carry generation network and hence they are the fastest types of adder that had been created and developed. Most common types of parallel prefix adder are Brent Kung and Kogge Stone adders. The performances of these two adders in terms of worst case delay and transistor count and power consumption studied and an analysis of the same is presented. Utilizing the same to design and implement the multiplier using PPA is performed in this paper.