A novel approach to accurate timing verification using RTL descriptions

Abstract

Timing verification is a critical part of VLSI circuit design. A new approach to timing verification using Register Transfer Level (RTL) descriptions is presented, which eliminates false paths that occur due to (i) redundancy, (ii) reconvergent fanout or (iii) control signal constraints, and generates a test for the critical paths. High level instructions of the circuit are used to test for any timing violations. An algorithm to identify a minimal set of instructions that tests the circuit for all timing errors in valid paths is proposed. Results are presented based on an implementation of the algorithm in LISP programming language on a TI Explorer machine.