Abstract
In most of digital systems, which require to have high level of resolution, time for digital converter is among the most significant blocks. Time difference amplifier (TDA) is utilized in time to digital converter in order to increase the level of accuracy. In this article, an all-digital TDA is suggested. The proposed TDA consumes delay lines with variation delay for amplifying. The proposed circuit is designed and simulated in 65 nm CMOS technology and obtain gain of six and chip areas about 0.002 mm2. The maximum calculated addition error is about 5%. The TDA harnesses 0.74 mW power under 1.1 V supply voltage.
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