A Novel Algorithmic Approach for Efficient Realization of 2-D-DCT Architecture for HEVC

Abstract

Low power realization of high efficiency video coding (HEVC) standard, which has found widespread application in mobile devices, tablets, and high-definition televisions, calls for an efficient approximation of discrete cosine transform (DCT) technique. In this paper, a novel algorithm is proposed to determine the minimum number of low-frequency DCT coefficients required for transform and quantization block in HEVC. Moreover, it introduces hardware efficient 1-D architectures for 4, 8, 16, and 32-point DCT, that make use of the proposed algorithm and conform to the HEVC standard. When these architectures are extended to the HEVC test model (HM), it leads to a minor reduction of PSNR (<;0.15 dB) and a slight increase in bitrate (<;1.5%). The encoding time of HM encoder is reduced up to 16.02% and produces the rate-distortion performance comparable to the reference algorithm. A new memory efficient addressing scheme for transpose memory is presented for 2D-DCT. The proposed 2D-DCT architecture has a low power dissipation and energy consumption of 8.62 mW and 1.77 pJ respectively and can process at least sixty 8K ($7630\times 4830$ ) frames/s. Such architecture with low power and energy characteristics can be integrated into a real-time HEVC encoder for portable consumer electronic products.