A novel 6H-SiC power DMOSFET with implanted p-well spacer

Abstract

In this letter, we utilize a lower thermal budget with an aluminum doped p-well to minimize the effect of step bunching and a new structural design with deep spacer implants to prevent the JFET pinching action at small p-well spacings (5 /spl mu/m) in planar vertical double implanted MOSFET (DIMOS) devices fabricated on 6H-SiC. A specific ON-resistance of 42 m/spl Omega/-cm/sup 2/ (further reducible by 35% through simple design modification), which represents a 100% reduction over devices which did not receive the spacer implants, is observed on the 2-/spl mu/m channel devices. This novel scheme will allow increased packing densities for high power applications using the DIMOS structure in SiC.