A Novel 3D NOR Flash With Single-Crystal Silicon Channel: Devices, Integration, and Architecture

Abstract

A novel 3D NOR memory array with single-crystal silicon channel, high-density and fast-read was proposed and fabricated. The proposed 3D NOR memory is investigated in terms of device structure, integration scheme, and circuit architecture. To obtain single-crystal silicon channel for 3D NOR, 1) vertical flash devices were presented, 2) a stack with multiple doped epitaxial Si layers was used for making the vertical devices, and 3) unlike 3D NAND, bit-line planes, source-line planes and vertical word-lines were utilized. Due to the use of single-crystal silicon channels, our memory devices have large read currents of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$110 ~\mu \text{A}/\mu \text{m}$ </tex-math></inline-formula> . Through programming/erasing tests, the programming speed of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$10 ~\mu \text{s}$ </tex-math></inline-formula> and erasing speed of 100 ms were obtained, which are comparable to that of the 2D NOR Flash with single-crystal silicon channels.