Abstract
Here, this paper completely examines the crosstalk noise of Through-Silicon-Vias (TSVs) in high speed operations by means of a novel 3-Dimensional-IC Test structural design. In order to decline the crosstalk, the fast rise time devices have to be circumvented except they are essential for performance in some certain circuit parts. It must be noted that this system simultaneously examines the TSVs and the memory and does not require spending additional area for a test pattern generator in case of the TSV test. With the intention of reprocessing the test patterns of new-fangled memory BIST, the value of “data” or “address” need to be fixed to some specific values. In accordance with the outcomes of the TSV grouping, here also implemented a high-efficiency, low-area-overhead TSV test structural design. The amount of test cycles essential for the purpose of finding failing TSVs and regulate the fault category effectively than that in related work.
Sign-in/Register to access full text options 
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callMore From: International Journal of Engineering & Technology
Disclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
