Abstract
In this article, a novel 3.3-kV integrated emitter turn-off thyristor (IETO) with single-gate controlling is proposed. Unlike the conventional emitter turn-off thyristor (ETO) using external MOSFETs, the IETO integrates the MOSFETs monolithically to switch ON and OFF. By featuring a P-layer beneath the trench of the carrier store trench bipolar transistor (CSTBT) to form self-biased pMOSs, the IETO clamps the potential of the P-layer, which shields the potential of the N-layer (carrier-stored layer), to reduce the saturation current. Due to the “self-clamping” effect, the high reverse voltage is sustained by the P-layer/N-drift junction, which makes the breakdown voltage (BV) independent of the dose of the N-layer. Then, the N-layer can be heavily doped to reduce V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ON</sub> without sacrificing the BV. TCAD simulation is compared with the CSTBT, which has the same controllability as the IETO and indicates that under the same level of BV, V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ON</sub> of the IETO is reduced by 0.12 V at E <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">OFF</sub> ≈ 8.5 mJ/cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> , and the E <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">OFF</sub> is 51.1% lower at V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ON</sub> ≈1.45 V. Moreover, the saturation current density is also reduced by 12.2%.
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