A novel 2.2 Gbps LVDS driver circuit design based on 0.35 μm CMOS

Abstract

This paper presents a novel high-speed low voltage differential signaling (LVDS) driver design for point-to-point communication. The switching noise of the driver was greatly suppressed by adding a charge/discharge circuit and the operating frequency of the circuit was also increased. A simple and effective common-mode feedback circuit was added to stabilize the output common-mode voltage. The proposed driver was implemented in a standard 0.35 μm CMOS process with a die area of 0.15 mm2. The test result shows that the proposed driver works well at 2.2 Gbps with power consumption of only 23 mW and 21.35 ps peak-to-peak jitter under a 1.8 V power supply.