A normalized-area measure for VLSI layouts

Abstract

A figure of merit called normalized-area, is introduced for the purpose of evaluating layouts for VLSI networks. This measure is distinctly different from the existing VLSI measures in two major aspects: (1) it expresses the utilization of the layout area by revealing the constant factor hidden in its asymptotic area-complexity; and (2) it distinguishes between node and wire sizes. Normalized-area is valuable in evaluating alternative layouts for a given structure as well as in analyzing the area utilization of a particular layout for that structure in an absolute sense. An analysis of the normalized-area of the layout schemes for regular structures proposed in the literature shows that most of these schemes are infeasible in practice. Array realizations for several well-known regular structures are used to demonstrate the usefulness of the normalized-area measure. Some practical guidelines for placement and routing to achieve good area utilization in a VLSI chip are presented. >