Abstract
AbstractIn this paper, we will newly define the fixed‐control testability as the property of the data paths for which the hierarchical test generation is easy; and based on it we will propose a design for testability (DFT) method for register transfer level (RTL) circuits. In the proposed method, since it is based on the hierarchical test generation using combinational test generation method and nonscan design, the test generation time and test execution time can be shortened drastically compared to the full‐scan design method, and the test at real operation speed (at‐speed test) is possible; and the complete fault detection efficiency can be guaranteed. Moreover, the effectiveness of the proposed method will be shown by experiments using benchmark circuits. © 2003 Wiley Periodicals, Inc. Electron Comm Jpn Pt 3, 86(10): 43–55, 2003; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/ecjc.10119
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