A Non-Redundant Latch With Key-Node-Upset Obstacle of Beneficial Efficiency for Harsh Environments Applications

Abstract

With the scaling down of process, single event upset has been a critical issue for integrated circuits. It is much more likely to occur multiple-node upsets (MNUs) in CMOS ICs in advanced technology. However, the problem remains unsolved because of the lack of efficient methods. In this article, a non-redundant triple-node-upset(TNU)-tolerant latch with high reliability is proposed in 28 nm CMOS technology. The proposed latch named KOBE reduces the number of inner-sensitive nodes as well as the redundancy of the TNU-tolerant latch. In simulations, the proposed KOBE latch performs faster and lower power with higher reliability than most of the TNU-tolerant latches proposed before. The post-layout parasitic extracted simulations show that the proposed KOBE latch has an average improvement of 52.5% in a Power-Area-Delay Product (PADP) compared with the recently reported TNU-hardened latch at a supply voltage of 0.9 V, a working temperature of 27 °C. What’s more, by changing the working voltage and temperature, it is proved that the proposed KOBE latch has a better performance in a harsh environment. The results show that the proposed KOBE latch is of high beneficial efficiency and high reliability, thus can be used in safety-critical applications.