Abstract

It is presented an analytic non-linear method for global placement of cells in circuits based on Dynamic Systems Theory, also known as Chaotic Systems. The related developed tool is called Chaotic Place. The two-dimensional structure of the cells of a circuit was obtained by the reconstruction of a Strange Attractor (Takens' Theorem). The experiment was tested in FPGAs using the “FPGA Place-and-Route Challenge” benchmarks. For comparison of results, the Half-Perimeter-Wire-Length (HPWL) was used as a metric and focus. The experiment results show a 6% reduction in wirelength, in average, when compared to the state-of-the-art placement tools for homogeneous FPGAs.

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